SH7101 Datasheet, PDF (306/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Watchdog Timer
9.4.4 Timing of Setting the Overflow Flag (OVF)
In interval timer mode, when TCNT overflows, the OVF bit of TCSR is set to 1 and an interval
timer interrupt (ITI) is simultaneously requested. Figure 9.4 shows this timing.
φ
TCNT
Overflow signal
(internal signal)
H'FF H'00
OVF
Figure 9.4 Timing of Setting OVF
9.4.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)
When TCNT overflows in watchdog timer mode, the WOVF bit of RSTCSR is set to 1 and a
WDTOVF signal is output. When the RSTE bit in RSTCSR is set to 1, TCNT overflow enables an
internal reset signal to be generated for the entire chip. Figure 9.5 shows this timing.
φ
TCNT
Overflow signal
(internal signal)
H'FF H'00
WOVF
Figure 9.5 Timing of Setting WOVF
Rev.2.00 Sep. 27, 2007 Page 272 of 448
REJ09B0394-0200