SH7101 Datasheet, PDF (54/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
2.4.2 Addressing Modes
Table 2.8 describes addressing modes and effective address calculation.
Table 2.8 Addressing Modes and Effective Addresses
Addressing
Mode
Direct register
addressing
Indirect register
addressing
Instruction
Format
Effective Address Calculation
Equation
Rn
The effective address is register Rn. (The operand ⎯
is the contents of register Rn.)
@Rn
The effective address is the contents of register Rn
Rn.
Rn
Rn
Post-increment
indirect register
addressing
@Rn+
The effective address is the contents of register
Rn.
A constant is added to the content of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation.
Rn
Rn
Rn + 1/2/4 ₊
1/2/4
Rn
(After the
instruction
executes)
Byte:
Rn + 1 → Rn
Word:
Rn + 2 → Rn
Longword:
Rn + 4 → Rn
Pre-decrement
indirect register
addressing
@-Rn
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for
a byte operation, 2 for a word operation, and 4 for
a longword operation.
Rn
Rn – 1/2/4 _–
Rn – 1/2/4
1/2/4
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn – 4 → Rn
(Instruction is
executed with
Rn after this
calculation)
Rev.2.00 Sep. 27, 2007 Page 20 of 448
REJ09B0394-0200