SH7101 Datasheet, PDF (27/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Figure 9.2
Figure 9.3
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Figure 9.5
Figure 9.6
Figure 9.7
Figure 9.8
Figure 9.9
Operation in Watchdog Timer Mode ..................................................................... 270
Operation in Interval Timer Mode ......................................................................... 271
Timing of Setting OVF........................................................................................... 272
Timing of Setting WOVF....................................................................................... 272
Writing to TCNT and TCSR .................................................................................. 273
Writing to RSTCSR ............................................................................................... 274
Contention between TCNT Write and Increment................................................... 275
Example of System Reset Circuit Using WDTOVF Signal ................................... 276
Section 10 Serial Communication Interface (SCI)
Figure 10.1 Block Diagram of SCI............................................................................................ 278
Figure 10.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)................................................. 296
Figure 10.3 Receive Data Sampling Timing in Asynchronous Mode ....................................... 298
Figure 10.4 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode)............................................................................................ 299
Figure 10.5 Sample SCI Initialization Flowchart ...................................................................... 300
Figure 10.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) ................................................... 301
Figure 10.7 Sample Serial Transmission Flowchart .................................................................. 302
Figure 10.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................. 303
Figure 10.9 Sample Serial Reception Data Flowchart (1) ......................................................... 305
Figure 10.9 Sample Serial Reception Data Flowchart (2) ......................................................... 306
Figure 10.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) ........................................... 308
Figure 10.11 Sample Multiprocessor Serial Transmission Flowchart ......................................... 309
Figure 10.12 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)............................... 310
Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (1)......................................... 311
Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (2)......................................... 312
Figure 10.14 Data Format in Clocked Synchronous Communication (For LSB-First) ............... 313
Figure 10.15 Sample SCI Initialization Flowchart ...................................................................... 314
Figure 10.16 Sample SCI Transmission Operation in Clocked Synchronous Mode ................... 316
Figure 10.17 Sample Serial Transmission Flowchart .................................................................. 317
Figure 10.18 Example of SCI Operation in Reception ................................................................ 318
Figure 10.19 Sample Serial Reception Flowchart ....................................................................... 319
Figure 10.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ....... 321
Section 11 A/D Converter
Figure 11.1 Block Diagram of A/D Converter (For One Module) ............................................ 326
Rev.2.00 Sep. 27, 2007 Page xxvii of xxxiv
REJ09B0394-0200