SH7101 Datasheet, PDF (419/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 16 RAM
16. RAM
This LSI has an on-chip high-speed static RAM. The on-chip RAM is connected to the CPU by a
32-bit data bus, enabling 8, 16, or 32-bit width access to data in the on-chip RAM. Data in the on-
chip RAM can always be accessed in one cycle, providing high-speed access that makes this RAM
ideal for use as a program area, stack area, or data area. The contents of the on-chip RAM are
retained in both sleep and standby modes.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control
register (SYSCR). For details on the system control register (SYSCR), refer to section 17.2.2,
System Control Register (SYSCR).
Product Type
SH7101
Type of ROM
Mask ROM
RAM Capacity
2 kbytes
RAM Address
H'FFFFF800 to
H'FFFFFFFF
16.1 Usage Note
• Module Standby Mode Setting
RAM can be enabled/disabled by the module standby control register. The initial value enables
RAM operation. RAM access is disabled by setting the module standby mode. For details, see
section 17, Power-Down Modes.
RAM0200A_000020030200
Rev.2.00 Sep. 27, 2007 Page 385 of 448
REJ09B0394-0200