SH7101 Datasheet, PDF (432/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Power-Down Modes
Oscillator
CK
NMI input
NMIE bit
SSBY bit
LSI state ^Program
NMI
exception
Exception
execution state _handling service routine
Software
standby mode
Oscillation WDT NMI exception
start time setting time handling
Oscillation stabilization
time
Figure 17.2 NMI Timing in Software Standby Mode
17.3.3 Module Standby Mode
Module standby mode can be set for individual on-chip peripheral functions.
When the corresponding MSTP bit in MSTCR is set to 1, module operation stops at the end of the
bus cycle and a transition is made to module standby mode. The CPU continues operating
independently.
When the corresponding MSTP bit is cleared to 0, module standby mode is cleared and the
module starts operating at the end of the bus cycle. In module standby mode, the internal states of
modules are initialized.
After reset clearing, the SCI, MTU, CMT, and A/D converter are in module standby mode.
When an on-chip peripheral module is in module standby mode, read/write access to its registers is
disabled.
Rev.2.00 Sep. 27, 2007 Page 398 of 448
REJ09B0394-0200