SH7101 Datasheet, PDF (247/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Multi-Function Timer Pulse Unit (MTU)
TCNT write cycle
T1 T2
Pφ
Address
TCNT_2 address
Write signal
TCNT_2
TGR2A_2 to
TGR2B_2
Ch2 compare-
match signal A/B
TCNT_1 input
clock
TCNT_1
H'FFFE
H'FFFF
N
TCNT_2 write data
H'FFFF
N+1
Disabled
M
TGRA_1
Ch1 compare-
match signal A
TGRB_1
Ch1 input capture
signal B
TCNT_0
M
N
M
P
TGRA_0 to
TGRD_0
Ch0 input capture
signal A to D
Q
P
Figure 8.78 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection
Rev.2.00 Sep. 27, 2007 Page 213 of 448
REJ09B0394-0200