SH7101 Datasheet, PDF (384/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. Compare Match Timer (CMT)
12.5.2 Contention between CMCNT Word Write and Incrementation
If an increment occurs during the T2 state of the CMCNT counter word write cycle, the counter
write has priority, so no increment occurs. Figure 12.7 shows the timing.
CMCNT write cycle
T1 T2
Pφ
Address
CMCNT
Internal write
signal
CMCNT
input clock
CMCNT
N
M
CMCNT write data
Figure 12.7 CMCNT Word Write and Increment Contention
Rev.2.00 Sep. 27, 2007 Page 350 of 448
REJ09B0394-0200