SH7101 Datasheet, PDF (358/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Serial Communication Interface (SCI)
10.8.5 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
10.8.6 Cautions on Clocked Synchronous External Clock Mode
1. Set TE = RE = 1 only when external clock SCK is 1.
2. Do not set TE = RE = 1 until at least four Pφ clocks after external clock SCK has changed
from 0 to 1.
3. When receiving, RDRF is 1 when RE is cleared to 0 after 2.5–3.5 Pφ clocks from the rising
edge of the RxD D7 bit SCK input, but copying to RDR is not possible.
10.8.7 Caution on Clocked Synchronous Internal Clock Mode
When receiving, RDRF is 1 when RE is cleared to 0 after 1.5 Pφ clocks from the rising edge of the
RxD D7 bit SCK output, but copying to RDR is not possible.
Rev.2.00 Sep. 27, 2007 Page 324 of 448
REJ09B0394-0200