SH7101 Datasheet, PDF (90/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

5. Exception Processing
Exception Sources
Vector Numbers Vector Table Address Offset
Trap instruction (user vector)
32
:
63
H'00000080 to H'00000083
:
H'000000FC to H'000000FF
Interrupts IRQ0
64
H'00000100 to H'00000103
IRQ1
65
H'00000104 to H'00000107
IRQ2
66
H'00000108 to H'0000010B
IRQ3
67
H'0000010C to H'0000010F
Reserved by system 68
H'00000110 to H'00000113
Reserved by system 69
H'00000114 to H'00000117
Reserved by system 70
H'00000118 to H'0000011B
Reserved by system 71
H'0000011C to H'0000011F
On-chip peripheral module *
72
:
255
H'00000120 to H'00000124
:
H'000003FC to H'000003FF
Note: * The vector numbers and vector table address offsets for each on-chip peripheral
module interrupt are given in section 6, Interrupt Controller (INTC), and table 6.2,
Interrupt Exception Processing Vectors and Priorities.
Table 5.4 Calculating Exception Processing Vector Table Addresses
Exception Source
Vector Table Address Calculation
Resets
Vector table address = (vector table address offset)
= (vector number) × 4
Address errors, interrupts,
instructions
Vector table address = VBR + (vector table address offset)
= VBR + (vector number) × 4
Notes: 1. VBR: Vector base register
2. Vector table address offset: See table 5.3.
3. Vector number: See table 5.3.
Rev.2.00 Sep. 27, 2007 Page 56 of 448
REJ09B0394-0200