SH7101 Datasheet, PDF (52/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
Multiply/Multiply-and-Accumulate Operations: 16-bit × 16-bit → 32-bit multiply operations
are executed in one to two states. 16-bit × 16-bit + 64-bit → 4-bit multiply-and-accumulate
operations are executed in two to three states. 32-bit × 32-bit → 64-bit multiply and 32-bit × 32-bit
+ 64-bit → 64-bit multiply-and-accumulate operations are executed in two to four states.
T Bit: The T bit in the status register changes according to the result of the comparison. Whether a
conditional branch is taken or not taken depends upon the T bit condition (true/false). The number
of instructions that change the T bit is kept to a minimum to improve the processing speed.
Table 2.4 T Bit
CPU of This LSI
CMP/GE
BT
BF
R1,R0
TRGET0
TRGET1
ADD
CMP/EQ
BT
#−1,R0
#0,R0
TRGET
Description
Example of Conventional CPU
T bit is set when R0 ≥ R1. The
program branches to TRGET0
when R0 ≥ R1 and to TRGET1
when R0 < R1.
CMP.W
BGE
BLT
R1,R0
TRGET0
TRGET1
T bit is not changed by ADD. T bit is SUB.W #1,R0
set when R0 = 0. The program
branches if R0 = 0.
BEQ TRGET
Immediate Data: Byte (8-bit) immediate data is located in an instruction code. Word or longword
immediate data is not located in instruction codes but in a memory table. An immediate data
transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with
displacement.
Table 2.5 Immediate Data Accessing
Classification CPU of This LSI
8-bit immediate MOV
#H'12,R0
16-bit immediate MOV.W
.DATA.W
@(disp,PC),R0
.................
H'1234
32-bit immediate MOV.L
.DATA.L
@(disp,PC),R0
.................
H'12345678
Note: @(disp, PC) accesses the immediate data.
Example of Conventional CPU
MOV.B #H'12,R0
MOV.W #H'1234,R0
MOV.L #H'12345678,R0
Rev.2.00 Sep. 27, 2007 Page 18 of 448
REJ09B0394-0200