SH7101 Datasheet, PDF (433/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Power-Down Modes
17.4 Usage Notes
17.4.1 I/O Port Status
When a transition is mode to software standby mode while the port high-impedance bit (HIZ) in
SBYCR is 0, I/O port states are retained. Therefore, there is no reduction in current consumption
for the output current when a high-level signal is output.
17.4.2 Current Consumption during Oscillation Stabilization Wait Period
Current consumption increases during the oscillation stabilization wait period.
17.4.3 On-Chip Peripheral Module Interrupt
Relevant interrupt operations cannot be performed in module standby mode. Consequently, if the
CPU enters module standby mode while an interrupt has been requested, it will not be possible to
clear the CPU interrupt source.
Interrupts should therefore be disabled before entering module standby mode.
17.4.4 Writing to MSTCR1 and MSTCR2
MSTCR1 and MSTCR2 should only be written to by the CPU.
Rev.2.00 Sep. 27, 2007 Page 399 of 448
REJ09B0394-0200