SH7101 Datasheet, PDF (155/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Multi-Function Timer Pulse Unit (MTU)
Table 8.25 TIORL_4 (channel 4)
Description
Bit 3 Bit 2 Bit 1 Bit 0 TGRC_4
IOC3 IOC2 IOC1 IOC0 Function
TIOC4C Pin Function
0
0
0
0
Output
Output disabled
1
compare
Initial output is 0
register*
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
X
0
0
Input
Input capture at rising edge
1
capture
Input capture at falling edge
register
1
X
Input capture at both edges
Legend:
X: Don't care
Note: * When the BFA bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev.2.00 Sep. 27, 2007 Page 121 of 448
REJ09B0394-0200