SH7101 Datasheet, PDF (139/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

TIORL_0, TIORL_3, TIORL_4
Bit Bit Name Initial value R/W
7
IOD3
0
R/W
6
IOD2
0
R/W
5
IOD1
0
R/W
4
IOD0
0
R/W
3
IOC3
0
R/W
2
IOC2
0
R/W
1
IOC1
0
R/W
0
IOC0
0
R/W
8. Multi-Function Timer Pulse Unit (MTU)
Description
I/O Control D0 to D3
Specify the function of TGRD.
When the TGRD is used as a buffer register of the
TGRB, this setting is invalid and input capture/output
compare is not generated.
See the following tables.
TIORL_0: Table 8.12
TIORL_3: Table 8.20
TIORL_4: Table 8.24
I/O Control C0 to C3
Specify the function of TGRC.
When the TGRC is used as a buffer register of the
TGRA, this setting is invalid and input capture/output
compare is not generated.
See the following tables.
TIORL_0: Table 8.13
TIORL_3: Table 8.21
TIORL_4: Table 8.25
Rev.2.00 Sep. 27, 2007 Page 105 of 448
REJ09B0394-0200