SH7101 Datasheet, PDF (228/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Multi-Function Timer Pulse Unit (MTU)
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is
set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare
match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The
MTU has 16 input capture/compare match interrupts, four each for channels 0, 3, and 4, and two
each for channels 1 and 2.
Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the
TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt
request is cleared by clearing the TCFV flag to 0. The MTU has five overflow interrupts, one for
each channel.
Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the
TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt
request is cleared by clearing the TCFU flag to 0. The MTU has two underflow interrupts, one
each for channels 1 and 2.
8.5.2 A/D Converter Activation
The A/D converter can be activated by the TGRA input capture/compare match in each channel.
If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a
TGRA input capture/compare match on a particular channel, a request to start A/D conversion is
sent to the A/D converter. If the MTU conversion start trigger has been selected on the A/D
converter at this time, A/D conversion starts.
In the MTU, a total of five TGRA input capture/compare match interrupts can be used as A/D
converter conversion start sources, one for each channel.
Rev.2.00 Sep. 27, 2007 Page 194 of 448
REJ09B0394-0200