SH7101 Datasheet, PDF (350/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Serial Communication Interface (SCI)
Synchroniza-
tion clock
Serial data
Transfer
direction
Bit 0 Bit 1
Bit 0 Bit 4 Bit 5
TDRE
TEND
TXI interrupt
request
generated
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
processing routine
TXI interrupt
request
generated
1 frame
Bit 6 Bit 7
TEI interrupt
request
generated
Figure 10.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
Rev.2.00 Sep. 27, 2007 Page 316 of 448
REJ09B0394-0200