SH7101 Datasheet, PDF (385/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. Compare Match Timer (CMT)
12.5.3 Contention between CMCNT Byte Write and Incrementation
If an increment occurs during the T2 state of the CMCNT byte write cycle, the counter write has
priority, so no increment of the write data results on the side on which the write was performed.
The byte data on the side on which writing was not performed is also not incremented, so the
contents are those before the write.
Figure 12.8 shows the timing when an increment occurs during the T2 state of the CMCNTH write
cycle.
CMCNT write cycle
T1 T2
Pφ
Address
CMCNTH
Internal write
signal
CMCNT input
clock
CMCNTH
N
M
CMCNTL
X
CMCNTH write data
X
Figure 12.8 CMCNT Byte Write and Increment Contention
Rev.2.00 Sep. 27, 2007 Page 351 of 448
REJ09B0394-0200