SH7101 Datasheet, PDF (75/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
2.6 Processing States
2.6.1 State Transitions
The CPU has four processing states: reset, exception processing, program execution and power-
down. Figure 2.4 shows the transitions between the states.
From any state
when RES = 0
From any state
when RES = 1
and MRES = 0
Power-on reset state
RES = 0
Manual reset state
When a power-on reset
or manual reset
occurred by WDT
RES = 1
Exception
processing state
RES = 1,
MRES = 1
Exception
processing
source
occurs
Exception
processing
ends
Reset state
NMI or IRQ
interrupt occurs
Program execution state
SSBY bit cleared
for SLEEP
instruction
SSBY bit set
for SLEEP
instruction
Sleep mode
Software standby mode
Power-down state
Figure 2.4 Transitions between Processing States
Rev.2.00 Sep. 27, 2007 Page 41 of 448
REJ09B0394-0200