SH7101 Datasheet, PDF (251/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Multi-Function Timer Pulse Unit (MTU)
8.7.16 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 8.82 shows the operation timing when a TGR compare match is specified as the clearing
source, and when H'FFFF is set in TGR.
Pφ
TCNT input
clock
TCNT
Counter clear
signal
TGF
H'FFFF
H'0000
TCFV
Disabled
Figure 8.82 Contention between Overflow and Counter Clearing
Rev.2.00 Sep. 27, 2007 Page 217 of 448
REJ09B0394-0200