SH7101 Datasheet, PDF (109/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Interrupt Controller (INTC)
Initial
Bit
Bit Name Value R/W Description
3
IPR3
0
2
IPR2
0
1
IPR1
0
0
IPR0
0
R/W These bits set priority levels for the corresponding
R/W
interrupt source.
R/W
0000: Priority level 0 (lowest)
R/W
0001: Priority level 1
0010: Priority level 2
0011: Priority level 3
0100: Priority level 4
0101: Priority level 5
0110: Priority level 6
0111: Priority level 7
1000: Priority level 8
1001: Priority level 9
1010: Priority level 10
1011: Priority level 11
1100: Priority level 12
1101: Priority level 13
1110: Priority level 14
1111: Priority level 15 (highest)
Note: Name in the tables above is represented by a general name. Name in the list of register is,
on the other hand, represented by a module name.
6.4 Interrupt Sources
6.4.1 External Interrupts
There are three types of interrupt sources: NMI, IRQ, and on-chip peripheral modules. Each
interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest).
Giving an interrupt a priority level of 0 masks it.
NMI Interrupts: The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin
is detected by edge. Use the NMI edge select bit (NMIE) in the interrupt control register 1 (ICR1)
to select either the rising or falling edge. NMI interrupt exception processing sets the interrupt
mask level bits (I3 to I0) in the status register (SR) to level 15.
IRQ3 to IRQ0 Interrupts: IRQ interrupts are requested by input from pins IRQ0 to IRQ3. Set
the IRQ sense select bits (IRQ0S to IRQ3S) of the interrupt control register 1 (ICR1) and IRQ
edge select bit (IRQ0ES[1:0] to IRQ3ES[1:0]) of the interrupt control register 2 (ICR2) to select
low level detection, falling edge detection, or rising edge detection for each pin. The priority level
can be set from 0 to 15 for each pin using the interrupt priority register A (IPRA).
Rev.2.00 Sep. 27, 2007 Page 75 of 448
REJ09B0394-0200