SH7101 Datasheet, PDF (181/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Multi-Function Timer Pulse Unit (MTU)
Examples of Buffer Operation:
• When TGR is an output compare register
Figure 8.16 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the
value in buffer register TGRC is simultaneously transferred to timer general register TGRA.
This operation is repeated each time that compare match A occurs.
For details of PWM modes, see section 8.4.5, PWM Modes.
TCNT value
TGRB_0
TGRA_0
H'0000
H'0200
H'0450
TGRC_0 H'0200
Transfer
TGRA_0
H'0450
H'0200
H'0520
H'0450
H'0520
Time
TIOCA
Figure 8.16 Example of Buffer Operation (1)
Rev.2.00 Sep. 27, 2007 Page 147 of 448
REJ09B0394-0200