SH7101 Datasheet, PDF (74/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
Instruction
Instruction Code
Operation
Execu-
tion
States T Bit
STS MACH,Rn
0000nnnn00001010 MACH → Rn
1
⎯
STS MACL,Rn
0000nnnn00011010 MACL → Rn
1
⎯
STS PR,Rn
0000nnnn00101010 PR → Rn
1
⎯
STS.L MACH,@–Rn 0100nnnn00000010 Rn – 4 → Rn, MACH → (Rn) 1
⎯
STS.L MACL,@–Rn 0100nnnn00010010 Rn – 4 → Rn, MACL → (Rn) 1
⎯
STS.L PR,@–Rn
0100nnnn00100010 Rn – 4 → Rn, PR → (Rn)
1
⎯
TRAPA #imm
11000011iiiiiiii PC/SR → stack area, (imm × 4 8
⎯
+ VBR) → PC
Note: * The number of execution states before the chip enters sleep mode: The execution
states shown in the table are minimums. The actual number of states may be increased
when (1) contention occurs between instruction fetches and data access, or (2) when
the destination register of the load instruction (memory → register) equals to the
register used by the next instruction.
Rev.2.00 Sep. 27, 2007 Page 40 of 448
REJ09B0394-0200