SH7101 Datasheet, PDF (230/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Multi-Function Timer Pulse Unit (MTU)
Pφ
External
clock
TCNT input
clock
Falling edge
Rising edge
Falling edge
TCNT
N-1
N
N+1
Figure 8.56 Count Timing in External Clock Operation (Phase Counting Mode)
Output Compare Output Timing: A compare match signal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a compare match signal is generated, the output value set in TIOR is output at the output
compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match
signal is not generated until the TCNT input clock is generated.
Figure 8.57 shows output compare output timing (normal mode and PWM mode) and figure 8.58
shows output compare output timing (complementary PWM mode and reset synchronous PWM
mode).
Pφ
TCNT input
clock
TCNT
N
N+1
TGR
N
Compare
match signal
TIOC pin
Figure 8.57 Output Compare Output Timing (Normal Mode/PWM Mode)
Rev.2.00 Sep. 27, 2007 Page 196 of 448
REJ09B0394-0200