SH7101 Datasheet, PDF (322/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Serial Communication Interface (SCI)
Table 10.2 Relationships between N Setting in BRR and Effective Bit Rate B₀
Mode
Asynchronous mode
(n = 0)
Asynchronous mode
(n = 1 to 3)
Clocked synchronous
mode (n = 0)
Bit Rate
Pφ × 10⁶
B₀ = _{32 × 22n × (N + 1)}
Pφ × 10⁶
B₀ = _{32 × 22n+1 × (N + 1)}
Pφ × 10⁶
B₀ = _{4 × 22n × (N + 1)}
Error
Error (%) =
B₀
B₁
– 1^⎞⎠ × 100
Error (%) =
B₀
B₁
– 1^⎞⎠ × 100
⎯
Clocked synchronous
Pφ × 10⁶
mode (n = 1 to 3)
B₀ = _{4 × 22n+1 × (N + 1)}
⎯
Notes: B₀: Effective bit rate (bit/s) Actual transfer speed according to the register settings
B₁: Logical bit rate (bit/s) Specified transfer speed of the target system
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
Pφ: Peripheral clock operating frequency (MHz)
n : Determined by the SMR settings shown in the following tables.
SMR Setting
CKS1
CKS0
n
0
0
0
0
1
1
1
0
2
1
1
3
Table 10.3 shows sample N settings in BRR in normal asynchronous mode. Table 10.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 10.6 shows sample N
settings in BRR in clocked synchronous mode. For details, refer to section 10.4.2, Receive Data
Sampling Timing and Reception Margin in Asynchronous Mode. Tables 10.5 and 10.7 show the
maximum bit rates with external clock input.
Rev.2.00 Sep. 27, 2007 Page 288 of 448
REJ09B0394-0200