SH7101 Datasheet, PDF (319/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Serial Communication Interface (SCI)
10.3.7 Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared.
Initial
Bit Bit Name Value
7
TDRE
1
6
RDRF
0
5
ORER
0
R/W
R/(W)*
R/(W)*
R/(W)*
Description
Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
• Power-on reset or software standby mode
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data
can be written to TDR
[Clearing condition]
• When 0 is written to TDRE after reading TDRE = 1
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
• When serial reception ends normally and receive data
is transferred from RSR to RDR
[Clearing conditions]
• Power-on reset or software standby mode
• When 0 is written to RDRF after reading RDRF = 1
The RDRF flag is not affected and retains their previous
values when the RE bit in SCR is cleared to 0.
Overrun Error
[Setting condition]
• When the next serial reception is completed while
RDRF = 1
[Clearing conditions]
• Power-on reset or software standby mode
• When 0 is written to ORER after reading ORER = 1
The ORER flag is not affected and retains their previous
values when the RE bit in SCR is cleared to 0.
Rev.2.00 Sep. 27, 2007 Page 285 of 448
REJ09B0394-0200