SH7101 Datasheet, PDF (37/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

1.2 Internal Block Diagram
RES
WDTOVF
MD3
MD2
MD1
MD0
NMI
EXTAL
XTAL
PLLVcL
PLL
PLLCAP
PLLVss
FWP
VcL
VcL
Vcc
Vcc
Vcc
Vss
Vss
Vss
Vss
AVcc
AVcc
AVss
AVss
Mask ROM
32 kbytes
RAM
2 kbytes
CPU
Interrupt
controller
Bus state controller
Serial communication
interface
(×2 channels)
Compare match
timer
(×2 channels)
Multifunction timer
pulse unit
A/D Watchdog
converter timer
1. Overview
: Peripheral address bus (12 bits)
: Peripheral data bus (16 bits)
: Internal address bus (32 bits)
: Internal upper data bus (16 bits)
: Internal lower data bus (16 bits)
Figure 1.1 Internal Block Diagram of SH7101
Rev.2.00 Sep. 27, 2007 Page 3 of 448
REJ09B0394-0200