SH7101 Datasheet, PDF (105/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Initial
Bit Bit Name Value
13
IRQ1ES1 0
12
IRQ1ES0 0
11
IRQ2ES1 0
10
IRQ2ES0 0
9
IRQ3ES1 0
8
IRQ3ES0 0
7 to 0 ⎯
All 0
6. Interrupt Controller (INTC)
R/W Description
R/W This bit sets the IRQ1 interrupt request edge detection
R/W ^mode.
00: Interrupt request is detected on falling edge of IRQ1
input
01: Interrupt request is detected on rising edge of IRQ1
input
10: Interrupt request is detected on both of falling and
rising edge of IRQ1 input
11: Cannot be set
R/W This bit sets the IRQ2 interrupt request edge detection
R/W ^mode.
00: Interrupt request is detected on falling edge of IRQ2
input
01: Interrupt request is detected on rising edge of IRQ2
input
10: Interrupt request is detected on both of falling and
rising edge of IRQ2 input
11: Cannot be set
R/W This bit sets the IRQ3 interrupt request edge detection
R/W ^mode.
00: Interrupt request is detected on falling edge of IRQ3
input
01: Interrupt request is detected on rising edge of IRQ3
input
10: Interrupt request is detected on both of falling and
rising edge of IRQ3 input
11: Cannot be set
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev.2.00 Sep. 27, 2007 Page 71 of 448
REJ09B0394-0200