SH7101 Datasheet, PDF (183/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Multi-Function Timer Pulse Unit (MTU)
8.4.4 Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 counter clock upon overflow/underflow of
TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 8.30 shows the register combinations used in cascaded operation.
Table 8.30 Cascaded Combinations
Combination
Upper 16 Bits
Lower 16 Bits
Channels 1 and 2
TCNT_1
TCNT_2
Note: When phase counting mode is set for channel 1 or 2, the counter clock setting is invalid and
the counters operates independently in phase counting mode.
Example of Cascaded Operation Setting Procedure: Figure 8.18 shows an example of the
setting procedure for cascaded operation.
Cascaded operation
Set cascading
[1]
Start count
[2]
[1] Set bits TPSC2 to TPSC0 in the channel 1
TCR to B'111 to select TCNT_2 overflow/
underflow counting.
[2] Set the CST bit in TSTR for the upper and
lower channel to 1 to start the count
operation.
<Cascaded operation>
Figure 8.18 Cascaded Operation Setting Procedure
Rev.2.00 Sep. 27, 2007 Page 149 of 448
REJ09B0394-0200