SH7101 Datasheet, PDF (101/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Interrupt Controller (INTC)
Section 6 Interrupt Controller (INTC)
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU.
6.1 Features
• 16 levels of interrupt priority
• NMI noise canceler function
• Occurrence of interrupt can be reported externally (IRQOUT pin)
Figure 6.1 shows a block diagram of the INTC.
IRQOUT
NMI
IRQ0
IRQ1
IRQ2
IRQ3
MTU
CMT
A/D
SCI
WDT
I/O
Input
control
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
ICR1
ICR2
ISR
IPR
IPRA to IPRI
Module bus
Bus
interface
INTC
Legend:
MTU : Multifunction timer unit
I/O
: I/O port (Port output controller)
CMT : Compare match timer
ICR1, ICR2
: Interrupt control register
A/D : A/D converter
ISR
: IRQ status register
SCI : Serial communications interface IPRA, IPRD to IPRI : Interrupt priority registers A, D to I
WDT : Watchdog timer
SR
: Status register
Figure 6.1 INTC Block Diagram
Rev.2.00 Sep. 27, 2007 Page 67 of 448
REJ09B0394-0200