SH7101 Datasheet, PDF (237/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Multi-Function Timer Pulse Unit (MTU)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC is activated, the flag is cleared automatically. Figure 8.68 shows the timing
for status flag clearing by the CPU.
TSR write cycle
T1
T2
Pφ
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 8.68 Timing for Status Flag Clearing by the CPU
Rev.2.00 Sep. 27, 2007 Page 203 of 448
REJ09B0394-0200