SH7101 Datasheet, PDF (47/486 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
2.2.1 General Registers (Rn)
The sixteen 32-bit general registers (Rn) are numbered R0 to R15. General registers are used for
data processing and address calculation. R0 is also used as an index register. Several instructions
have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving
and recovering the status register (SR) and program counter (PC) in exception processing is
accomplished by referencing the stack using R15.
2.2.2 Control Registers
The control registers consist of three 32-bit registers: status register (SR), global base register
(GBR), and vector base register (VBR). The status register indicates processing states. The global
base register functions as a base address for the indirect GBR addressing mode to transfer data to
the registers of on-chip peripheral modules. The vector base register functions as the base address
of the exception processing vector area (including interrupts).
Status Register (SR):
Initial
Bit
Bit Name Value
R/W
31 to 10 ⎯
All 0
R/W
9
M
8
Q
7
I3
6
I2
5
I1
4
I0
3, 2
⎯
Undefined R/W
Undefined R/W
1
R/W
1
R/W
1
R/W
1
R/W
All 0
R/W
1
S
Undefined R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Used by the DIV0U, DIV0S, and DIV1 instructions.
Used by the DIV0U, DIV0S, and DIV1 instructions.
Interrupt mask bits.
Reserved
This bit is always read as 0. The write value should
always be 0.
S bit
Used by the MAC instruction.
Rev.2.00 Sep. 27, 2007 Page 13 of 448
REJ09B0394-0200