C508_01 Datasheet, PDF (99/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
6.2.2.3 Compare Function of Registers CRC, T2CC1 to T2CC3
The compare function of a timer/register combination can be described as follows. The
16-bit value stored in a Compare/Capture register is compared with the contents of the
timer register. lf the count value in the timer register matches the stored value, an
appropriate output signal is generated at a corresponding port pin, and an interrupt is
requested.
The contents of a compare register can be regarded as a “time stamp” at which a
dedicated output reacts in a predefined way (with either a positive or negative transition).
Variation of this “time stamp” somehow changes the wave of a rectangular output signal
at a port pin. As a variation of the duty cycle of a periodic signal, this may be used for
pulse width modulation as well as for a continually controlled generation of any kind of
square waveforms. Two Compare modes are implemented to cover a wide range of
possible applications.
The compare modes 0 and 1 are selected by bit T2CM in special function register
T2CON. In both compare modes, the new value arrives at the port pin 1 within the same
machine cycle in which the internal compare signal is activated.
The four registers CRC, T2CC1 to T2CC3 are multifunctional as they additonally provide
a capture, compare or reload capability (reload capability for CRC register only). A
general selection of the function is done in register CCEN. Please note that the compare
interrupt CC0 can be programmed to be negative or positive transition activated. The
internal compare signal (not the output signal at the port pin!) is active as long as the
timer 2 contents is equal to the one of the appropriate compare registers, and it has a
rising and a falling edge. Thus, when using the CRC register, it can be selected whether
an interrupt should be caused when the compare signal goes active or inactive,
depending on bit I3FR in T2CON. For the CC registers 1 to 3 an interrupt is always
requested when the compare signal goes active (see Figure 6-16).
6.2.2.3.1 Compare Mode 0
In mode 0, when the timer and compare register contents match, the output signal
changes from low to high. lt goes back to a low level on timer overflow. As long as
compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit
only, and not by the user. Writing to the port will have no effect. Figure 6-15 shows a
functional diagram of a port latch in compare mode 0. The port latch is directly controlled
by the two signals timer overflow and compare. The input line from the internal bus and
the write-to-latch line are disconnected when compare mode 0 is enabled.
Compare mode 0 is ideal for generating pulse width modulated output signals, which in
turn can be used for digital-to-analog conversion via a filter network or by the controlled
device itself (e.g. the inductance of a DC or AC motor). Mode 0 may also be used for
providing output clocks with initially defined period and duty cycle. This is the mode
which needs the least CPU time. Once set up, the output goes on oscillating without any
User’s Manual
6-34
2001-05