C508_01 Datasheet, PDF (127/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
Writing the CAPCOM Period/Offset/Compare Registers on-the-Fly
If Compare Timer 1 is running, then the period, offset or compare registers can be written
with modified values for generating new periods or duty cycles of the compare output
signals. For proper synchronization purposes, a special mechanism for updating of the
16-bit offset, period, and compare registers is implemented in the C508. This mechanism
is based on shadow latches. When new values for offset, period, or compare registers
have been written into the shadow latches, the real register update operation must be
initiated by setting bit STE1 (shadow transfer enable) in SFR CT1CON. When this bit is
set, the content of the shadow latches is transferred to the real registers when Compare
Timer 1 has reached its period value or zero value. This applies to both operating
modes 0 and 1.
When the register transfer has been executed, STE1 is reset by hardware. So the
software can recognize when the register transfer has occurred.
When Compare Timer 1 is started by setting the run bit CT1R the first time after reset, a
shadow register transfer into the real registers is automatically executed. In this case
STE1 must not be set.
Care must be taken when programming a new compare value. If the new compare value
is greater than or equal to the period value, the reload should be delayed till the next zero
match (Compare Timer 1 reaches 0000_H) instead of the approaching period match
(Compare Timer 1 reaches period value). This can be achieved by setting bit STE1 only
in the period match interrupt service routine.
If the desired compare value is less than the offset value, the COUT bits in COINI register
must be inverted first, before the reload is allowed.
User’s Manual
6-62
2001-05