C508_01 Datasheet, PDF (27/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Memory Organization
Reset initializes the stack pointer to location 07_H and increments it once to start from
location 08_H which is also the first register (R0) of register bank 1. Thus, if more than one
register bank is required, the SP should be initialized to a different location of the RAM
which is not used for data storage.
3.4
XRAM Operation
The XRAM in the C508 is a memory area that is logically located at the upper end of the
external data memory space, but is integrated on the chip. Because the XRAM is used
in the same way as external data memory, the same instruction types (MOVX) must be
used for accessing the XRAM.
3.4.1 XRAM Controller Access Control
Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to XRAM. XMAP0
is a general access enable/disable control bit and XMAP1 controls the external signal
generation during XRAM accesses.
Special Function Register SYSCON (Address B1_H)
Reset Value: XX10XX01_B
Bit No. MSB
LSB
7
6
5
4
3
2
1
0
B1_H
–
– _{EALE RMAP –}
– XMAP1XMAP0 SYSCON
The functions of the shaded bits are not described here.
Bit
XMAP1
XMAP0
–
User’s Manual
Function
XRAM visible access control
Control bit for RD/WR signals during XRAM accesses. If addresses are
outside the XRAM address range or if XRAM is disabled, this bit has no
effect.
XMAP1 = 0: The signals RD and WR are not activated during
accesses to the XRAM.
XMAP1 = 1: Ports 0, 2 and the signals RD and WR are activated
during accesses to XRAM. In this mode, address
and data information during XRAM accesses are
visible externally.
Global XRAM access enable/disable control
XMAP0 = 0: The access to XRAM is enabled.
XMAP0 = 1: The access to XRAM is disabled (default after
reset). All MOVX accesses are performed via the
external bus. Further, this bit is hardware protected.
Reserved bits for future use. Read by CPU returns undefined values.
3-3
2001-05