C508_01 Datasheet, PDF (242/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Power Saving Modes
9.4
Software Power Down Mode
In the software power-down mode, the RC oscillator, the on-chip oscillator which
operates with the XTAL pins, and the PLL are all stopped. Therefore, all functions of the
microcontroller are stopped and only the contents of the on-chip RAM, XRAM, and the
SFRs are maintained. The port pins, which are controlled by their port latches, output the
values that are held by their SFRs. The port pins which serve the alternative output
functions show the values they had at the end of the last cycle of the instruction which
initiated the power-down mode. ALE and PSEN are held at logic low level (see
Table 9-1).
In the power-down mode of operation, V_DD can be reduced to minimize power
consumption. It must be ensured, however, that V_DD is not reduced before the power-
down mode is invoked, and that V_DD is restored to its normal operating level before the
power-down mode is terminated.
The software power-down mode can be left either by an active reset signal or by a low
signal at one of the wake-up source pins. Using reset to leave power-down mode puts
the microcontroller with its SFRs into the reset state. Using either the P3.2/INT0 pin or
the P5.7/INT7 pin to exit power-down mode starts the RC oscillator, the on-chip
oscillator, and the PLL; and maintains the state of the SFRs, which have been frozen
when power-down mode was entered. Leaving power-down mode should not be done
before V_DD is restored to its nominal operating level.
9.4.1 Invoking Software Power Down Mode
The software power-down mode is entered by two consecutive instructions. The first
instruction must set the flag bit PDE (PCON.1) and must not set bit PDS (PCON.6). The
following instruction must set the start bit PDS (PCON.6) and must not set bit PDE
(PCON.1). The hardware ensures that a concurrent setting of both bits, PDE and PDS,
does not initiate the power-down mode. Bits PDE and PDS will automatically be cleared
after having been set and the value shown by reading one of these bits is always 0. This
double instruction is implemented to minimize the chance of unintentionally entering the
power-down mode which could possibly “freeze” the chip’s activity in an undesired
status.
PCON is not a bit-addressable register, so the above mentioned sequence for entering
the power down mode is obtained by byte-handling instructions, as shown in the
following example:
ORL PCON,#00000010B;set bit PDE, bit PDS must not be set
ORL PCON,#01000000B;set bit PDS, bit PDE must not be set, enter power down
The instruction that sets bit PDS is the last instruction executed before going into power-
down mode. When the double instruction sequence shown above is used, the power-
down mode can only be left by a reset operation. If the external wake-up from power-
User’s Manual
9-6
2001-05