C508_01 Datasheet, PDF (205/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
7.2
Interrupt Registers
Interrupt System
7.2.1 Interrupt Enable Registers
Each interrupt vector can be individually enabled or disabled by setting or clearing the
corresponding bit in the Interrupt Enable Registers IEN0, IEN1, IEN2 and IEN3. Register
IEN0 also contains the global disable bit (EA), which can be cleared to disable all
interrupts at once. Generally, all interrupt enable bits are cleared to 0 after reset; the
corresponding interrupts are disabled.
The SFR IEN0 contains the enable bits for the external interrupts 0 and 1, the timer
interrupts, and the USART interrupt.
Special Function Register IEN0 (Address A8_H)
Reset Value: 00_H
MSB
Bit No. AF_H
AE_H AD_H
AC_H
AB_H AA_H
LSB
A9_H A8_H
A8_H EA WDT ET2 ES ET1 EX1 ET0 EX0 IEN0
The shaded bits are not used for interrupt control.
Bit
Function
EA
Enable/disable all interrupts
If EA = 0, no interrupt will be acknowledged.
If EA = 1, each interrupt source is individually enabled or disabled by
setting or clearing its enable bit.
ET2
Timer 2 overflow/external reload interrupt enable
If ET2 = 0, the Timer 2 interrupt is disabled.
If ET2 = 1, the Timer 2 interrupt is enabled.
ES
Serial channel (USART) interrupt enable
If ES = 0, the Serial Channel Interrupt 0 is disabled.
If ES = 1, the Serial Channel Interrupt 0 is enabled.
ET1
Timer 1 overflow interrupt enable
If ET1 = 0, the Timer 1 interrupt is disabled.
If ET1 = 1, the Timer 1 interrupt is enabled.
EX1
External interrupt 1 enable
If EX1 = 0, the external interrupt 1 is disabled.
If EX1 = 1, the external interrupt 1 is enabled.
User’s Manual
7-7
2001-05