C508_01 Datasheet, PDF (230/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Fail Save Mechanisms
8.1.2 Watchdog Timer Control/Status Flags
The Watchdog Timer is controlled by two control flags (located in SFR IEN0 and IEN1)
and one status flag (located in SFR IP0).
Special Function Register IEN0 (Address A8_H)
Special Function Register IEN1 (Address B8_H)
Special Function Register IP0 (Address A9_H)
Reset Value: 00_H
Reset Value: X0000000_B
Reset Value: 00_H
MSB
Bit No. AF_H
AE_H AD_H
AC_H
AB_H AA_H
LSB
A9_H A8_H
A8_H EA WDT ET2 ES ET1 EX1 ET0 EX0 IEN0
Bit No. BF_H BE_H BD_H BC_H BB_H BA_H B9_H B8_H
B8_H
− SWDT EX6 EX5 EX4 EX3 EX2 EADC IEN1
Bit No. ₇
6
5
4
3
2
1
0
A9_H OWDS WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0 IP0
The shaded bits are not used for fail save control.
Bit
WDT
SWDT
WDTS
Function
Watchdog Timer refresh flag
Set to initiate a refresh of the Watchdog Timer. Must be set
before SWDT is set to prevent an unintentional refresh of the
Watchdog Timer.
Watchdog Timer Start flag
Set to activate the Watchdog Timer. If set after WDT has
been set, a Watchdog Timer refresh is performed.
Watchdog Timer Status flag
Set by hardware when a Watchdog Timer reset occurred.
Can be cleared and set by software.
Immediately after start, the Watchdog Timer is initialized to the reload value programmed
in WDTREL.0-WDTREL.6. Register WDTREL is cleared to 00_H after an external HW
reset, an Oscillator Watchdog power-on reset, or a Watchdog Timer reset. The lower
seven bits of WDTREL can be loaded by software at any time.
User’s Manual
8-4
2001-05