C508_01 Datasheet, PDF (244/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Power Saving Modes
Power Down
Mode
(1)
P3.2/INT0
or
P5.7/INT7
Latch
Phase
(2)
On-Chip Oscillator
Start-Up Phase
(3)
min. 10 µs
typ. 5 m s
Detailed Timing of Beginning of Phase 5
ALE
PSEN
P2
Invalid Address
P0
Invalid Address/Data
PLL Execution
Locked of interrupt
Phase at 007B_H
(4)
(5)
max. 1 m s RETI
Instruction
00_H
7B_H
1st Instr.
of ISR
MCT04089
Figure 9-1 Wake-up from Power Down Mode Procedure
When the power down-mode wake-up capability has been enabled (bit EWPD in SFR
PCON1 set) prior to entering power-down mode and bit WS in SFR PCON1 is cleared,
the power-down mode can be left via P3.2/INT0 while executing the following procedure:
1. In power-down mode, pin P3.2/INT0 must be held at high level.
2. Power-down mode is left when P3.2/INT0 goes low for at least 10 µs (latch phase).
The internal RC oscillator, the on-chip oscillator, and the PLL are started; the state of
pin P3.2/INT0 is internally latched; and P3.2/INT0 can be set again to high level if
required, after this delay. Thereafter, the Oscillator Watchdog unit controls the wake-
up procedure in its start-up phase.
3. The Oscillator Watchdog unit starts operation. Typically, the on-chip oscillator takes
about 5 ms to stabilize.
4. The PLL will be locked within 1ms after the on-chip oscillator clock is detected for
stable nominal frequency. Subsequently, the microcontroller starts again to initiate the
power down wake-up interrupt. The interrupt address of the first instruction to be
executed after wake-up is 007B_H. ALE and PSEN are in their power-down state up to
this time. At the end of Phase 4, the CPU processes the interrupt call and, during these
User’s Manual
9-8
2001-05