C508_01 Datasheet, PDF (116/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
CMSEL1 define which of these two outputs will be controlled by the CAPCOM channel.
In Figure 6-26 only the CCx signal is shown, but the same or the inverted waveform can
be generated at the COUTx outputs.
After reset all CCx/COUTx pins are at high level, driven by a weak pull-up. With the
programming of the CMSEL1 or CMSEL0 registers, all affected compare outputs are
switched to push-pull mode and start driving an initial level which is defined by the bits
in SFR COINI. In Figure 6-26, the upper five waveforms are assigned to a CCx pin with
the appropriate bit in COINI cleared while the lower five waveforms are assigned to a
CCx pin with the appropriate bit in COINI set.
When the count value of the Compare Timer 1 is incremented and the new value
matches the value stored in the corresponding compare register, the related compare
output changes its logic state. When the compare timer is reset to 0000_H the related
compare output changes its logic state again. With the scheme shown in Figure 6-26,
output waveforms with duty cycles between 0% and 100% can be generated. For a
compare register value of 0000_H, the output will remain at high level (COINI bit = 0) or
low level (COINI bit = 1), representing a duty cycle of 100%. If the value stored in the
compare register is greater than or equals to the value of the period register, a low level
(COINI bit = 0) or high level (COINI bit = 1) corresponds to a duty cycle of 0%.
Figure 6-27 shows the waveform generation in operating mode 0 when the offset
register has a value which is not equal 0000_H (example: CT1OFH/CT1OFL = 0002_H).
Using Compare Timer 1 with an offset value not equal 0 is used to generate single edge
aligned signals with a constant delay between one of the two signal transitions.
Compare Timer 1 always counts from 0000_H up to the value stored in CCP, if the value
in the offset register is not equal 0. With reset (count value 0000_H) of the Compare
Timer 1, the CCx and COUTx will always change their logic state. During the up-counting
phase, CCx will change the logic state when the compare timer value is equal to the
compare register value; and COUTx will change the logic state when the compare timer
value plus the offset value matches the value stored in the compare register.
In Figure 6-27 the waveforms a) and b) show an example for a waveform of two signals
with a constant delay of their rising edge. A compare register value of 3 is assumed.
Using inverted signal polarity (SFR COINI), signal c) can be generated at COUTx. If the
value in the offset register plus the value of the period register is less than or equal to the
value stored in the compare register, a static ‘1’ or a static ‘0’ (depending on COINI
content) will be generated at COUTx (see Figure 6-27 d) and e)). Therefore, CCx will
also stay at a static level if the compare register value is greater than the value stored in
the period register.
User’s Manual
6-51
2001-05