C508_01 Datasheet, PDF (115/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
6.3.2.2 CAPCOM Unit Operating Mode 0
Figure 6-26 shows the details of the CAPCOM unit timing in operating mode 0.
CT1 Value
CCP = 7
Period Reg.
7
6
5
7
6
5
4
4
4
Offset Reg.
CT1OFF = 0
3
2
1
3
2
1
3
2
1
Time
0
Start of CT1
0
0
Duty
Cycles:
(CC = 0)
100%
(CC = 1)
87.5%
(CC = 4)
50%
(CC ≥ 7)
"0"
0%
(CC = 0)
100%
(CC = 1)
87.5%
(CC = 4)
50%
(CC ≥ 7)
"1"
0%
CC : content of the CCxH/CCxL compare registers
CCP : content of the CCPH/CCPL period register
CC1O : content of the CT1OFH/CT1OFL offset register
MCT04067
Figure 6-26 Compare Timer 1 Mode 0
In the example above, Compare Timer 1 counts from 0000_H up to 0007_H (value stored
in CCPH/CCPL). The offset registers CT1OFH/CT1OFL have a value of 0000_H. If
programmed in compare mode, two output signals (CCx and COUTx) are assigned to
the related CAPCOM channel x. The mode select bits in the SFRs CMSEL0 and
User’s Manual
6-50
2001-05