C508_01 Datasheet, PDF (176/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
6.4.4 Details about Mode 0
Serial data enters and exits through RxD. TxD outputs the shift clock. Eight data bits are
transmitted/received with the LSB first. The baudrate is fixed at f_OSC/3.
Figure 6-43 shows a simplified functional diagram of the serial port in Mode 0. The
associated timing is illustrated in Figure 6-44.
Transmission is initiated by any instruction that uses SBUF as a destination register. The
“Write-to-SBUF” signal at S6P2 also loads a ‘1’ into the 9^th position of the transmit shift
register and tells the TX control block to commence a transmission. The internal timing
is such that one full machine cycle will elapse between “Write-to-SBUF”, and activation
of SEND.
SEND enables the output of the shift register to the alternative output function line of
P3.0, and also enables SHIFT CLOCK to the alternative output function line of P3.1.
SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6,
S1 and S2. At S6P2 of every machine cycle in which SEND is active, the contents of the
transmit shift register are shifted to the right one position.
As data bits shift out to the right, ‘0’s come in from the left. When the Most Significant Bit
(MSB) of the data byte is at the output position of the shift register, the ‘1’ that was initially
loaded into the 9^th position is just to the left of the MSB, and all positions to the left of that
contain ‘0’s. This condition flags the TX control block to do one last shift and then
deactivate SEND and set TI. Both of these actions occur at S1P1 of the 10^th machine
cycle after “Write-to-SBUF”.
Reception is initiated by the condition REN = 1 and RI = 0. At S6P2 of the next machine
cycle, the RX control unit writes the bits “1111 1110” to the receive shift register, and in
the next clock phase activates RECEIVE.
RECEIVE enables SHIFT CLOCK to the alternative output function line of P3.1. SHIFT
CLOCK makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of every
machine cycle in which RECEIVE is active, the contents of the receive shift register are
shifted to the left one position. The value that comes in from the right is the value that
was sampled at the P3.0 pin at S5P2 of the same machine cycle.
As data bit comes in from the right, ‘1’s shift out to the left. When the ‘0’ which was initially
loaded into the rightmost position arrives at the leftmost position in the shift register, it
flags the RX control block to do one last shift and load SBUF. At S1P1 of the 10^th
machine cycle after the write to SCON that cleared RI, RECEIVE is cleared and RI is set.
User’s Manual
6-111
2001-05