C508_01 Datasheet, PDF (144/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
The COMP unit has a 10-bit up-counter (Compare Timer 2, CT2) which starts counting
from 000_H up to the value stored in the period register and then is again reset. This
Compare Timer 2 operation is similar to the operating mode 0 of Compare Timer 1.
When the count value of CT2 matches the value stored in the compare registers
CMP2H/CMP2L, COUT3 toggles its logic state. When Compare Timer 2 is reset to 000_H,
COUT3 toggles again its logic state.
COUT3 is only an output pin. After a reset operation COUT3 drives a high level as
defined by the reset value (= 1) of bit COUT3I of SFR COINI. When Compare Timer 2 is
running (bit CT2R in SFR CT2CON is set), bit ECT2O in SFR CT2CON allows the
disconnection of COUT3 from Compare Timer 2 signal generation. In this case, the logic
value of COUT3I (bit COINI.7) is put to the COUT3 output. When ECT2O is set
thereafter, the Compare Timer 2 output signal is again switched to the COUT3 output.
In the combined multi-channel PWM modes and in the burst mode, the Compare Timer 2
output signal can also be switched to the CAPCOM output pins COUT0, COUT1, and
COUT3. In these modes, the polarity of the modulated output signal at COUT2-0 can be
inverted by setting bit COUTXI (COINI.6)
6.3.3.1 COMP Registers
The COMP unit has five SFRs which are listed in Table 6-8.
Table 6-8 Special Function Registers of the COMP Unit
Unit
Symbol
Description
Address
COMP
Compare
Unit
CT2CON
CP2L
CP2H
CMP2L
CMP2H
Compare Timer 2 control register
F1_H
Compare Timer 2 period register, low byte
D2_H
Compare Timer 2 period register, high byte D3_H
Compare Timer 2 Compare register, low byte D4_H
Compare Timer 2 Compare register, high byte D5_H
The Compare Timer 2 period and compare registers store a 10-bit value, organized in
two bytes. For proper synchronization purposes, these registers are not written directly.
Each value of a write operation to these registers is stored in shadow latches. The
transfer of these shadow latches into the real registers is synchronized with the Compare
Timer 2 value 000_H and controlled by bit STE2. When the period or compare value is
changed by writing the corresponding SFR, the setting of bit STE2 (CT2CON.5) enables
the write transfer of the shadow registers into the real registers. This shadow latch
transfer happens when the Compare Timer 2 reaches the count value 000_H the next time
after STE2 has been set. With the automatic transfer of the shadow latches to the real
registers, bit STE2 is reset by hardware. When the Compare Timer 2 period and
compare registers are initialized after reset, bit STE2 must also be set to enable the
shadow latch transfer when Compare Timer 2 is started the first time.
Note: Read operations with the Compare Timer 2 period and compare registers always
access the shadow registers and not the real registers.
User’s Manual
6-79
2001-05