C508_01 Datasheet, PDF (152/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Bit
BCERR
BCEN
BCM1
BCM0
On-Chip Peripheral Components
Function
Block commutation mode error flag
In block commutation mode BCERR is set in rotate right or rotate left
mode if after a transition at INTx all INTx inputs are at high or low
level. Additionally, in rotate right or rotate left mode a “wrong follower”
condition according to Table 6-10 can cause the setting of BCERR
(see description of bit BCEM).
If the block commutation interrupt is enabled (EBCE = 1), the setting
of BCERR will generate a CCU emergency interrupt. BCERR must be
reset by software.
Block commutation enable
If BCEN is set, the multi-channel PWM modes of the CAPCOM unit
as selected by the bits PWM1/PWM0 are enabled for operation.
Before BCEN bit is set, all required PWM Compare outputs should be
programmed to operate as compare outputs by writing the registers
CMSEL1/CMSEL0.
Multi-channel PWM mode output pattern selection
Additionally to bits PWM1 and PWM0, these two control bits select
the output signal pattern in all multi-channel PWM modes. The
detailed signal pattern information is given in Table 6-10 to
Table 6-13.
BCM1
0
0
1
1
BCM0
0
1
0
1
Function
Idle mode
Rotate right mode
Rotate left mode
Slow down mode
Note: When a multi-channel PWM mode is initiated the first time after reset, BCON must
be written twice: first write operation with bit BCEN cleared and all other bits set/
cleared as required (BCM1, 0 must be 0, 0 for idle mode), followed by a second
write operation with the same BCON bit pattern of the first write operation but with
BCEN set. After this second BCON write operation, Compare Timer 1 can be
started (setting CT1R in CT1CON) and thereafter BCM1, 0 can be put into another
mode than idle mode.
User’s Manual
6-87
2001-05