C508_01 Datasheet, PDF (225/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Interrupt System
Execution proceeds from that location until the RETI instruction is encountered. The
RETI instruction informs the processor that the interrupt routine is no longer in progress,
then pops the two top bytes from the stack and reloads the program counter. Execution
of the interrupted program continues from the point where it was stopped. Note that the
RETI instruction is very important because it informs the processor that the program left
the current interrupt priority level. A simple RET instruction would also have returned
execution to the interrupted program; but, it would have left the interrupt control system
thinking an interrupt was still in progress. In this case no interrupt of the same or lower
priority level would be acknowledged.
7.5
External Interrupts
The external interrupts 0 and 1 can be programmed to be level-activated or negative-
transition activated by setting or clearing bit ITx (x = 0 or 1), respectively, in register
TCON. If ITx = 0, external interrupt x is triggered by a detected low level at the INTx pin.
If ITx = 1, external interrupt x is negative edge-triggered. In this mode, if successive
samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt
request flag IEx in TCON is set. Flag bit IEx =1 then requests the interrupt.
If the external interrupt 0 or 1 is level-activated, the external source must hold the request
active until the requested interrupt is actually generated. Then, it must deactivate the
request before the interrupt service routine is completed, or else another interrupt will be
generated.
The external interrupts 2, 3, 7, 8, and 9 can be programmed to be either negative or
positive transition-activated by setting or clearing bits I2FR or I3FR in register T2CON or
bits I7FR, I8FR or I9FR in register EINT. If IxFR = 0 (x = 2, 3, 7, 8, or 9) then the external
interrupt x is negative transition-activated. If IxFR = 1, the external interrupt is triggered
by a positive transition.
The external interrupts 4, 5, and 6 are activated only by a positive transition.
As the external interrupt pins are sampled once in each machine cycle, an input high or
low should be held for at least three oscillator periods to ensure sampling. lf the external
interrupt is positive (negative) transition-activated, the external source must hold the
request pin low (high) for at least one cycle, and then hold it high (low) for at least one
cycle to ensure that the transition is recognized. In that way, the corresponding interrupt
request flag will be set (see Figure 7-7). The external interrupt request flags will
automatically be cleared by the CPU when the service routine is called.
User’s Manual
7-27
2001-05