C508_01 Datasheet, PDF (76/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
much lower current than p1; therefore, the pin may also be tied to ground, for
example, when used as input with logic low input level.
– The pull-up FET p3 is a p-channel type. It is activated only if the voltage at the port
pin is higher than approximately 1.0 to 1.5 V. This provides an additional pull-up
current if a logic high level shall be output at the pin (and the voltage is not forced
lower than approximately 1.0 to 1.5 V). However, this transistor is turned off if the
pin is driven to a logic low level; for example, when used as input. In this
configuration, only the weak pull-up FET p2 is active, which sources the current I_IL.
If, in addition, the pull-up FET p3 is activated, a higher current can be sourced (I_TL).
Thus, additional power consumption can be avoided if port pins are used as inputs
with a low level applied. However, the driving capability is stronger if a logic high
level is output.
The activating and deactivating of the four different transistors translates into four states
possible for the pins:
– Input low state (IL), p2 active only
– Input high state (IH) = steady output high state (SOH) p2 and p3 active
– Forced output high state (FOH), p1, p2 and p3 active
– Output low state (OL), n1 active
If a pin is used as input and a low level is applied, it will be in IL state; if a high level is
applied, it will switch to IH state.
If the latch is loaded with a ‘0’, the pin will be in OL state.
If the latch holds a ‘0’ and is loaded with a ‘1’, the pin will enter FOH state for two cycles
and then switch to SOH state. If the latch holds a ‘1’ and is reloaded with a ‘1’, no state
change will occur.
At the beginning of power-on reset, the pins will be in IL state (latch is set to ‘1’, voltage
level on pin is below of the trip point of p3). Depending on the voltage level and load
applied to the pin, it will remain in this state or will switch to IH (= SOH) state.
If it is used as output, the weak pull-up p2 will pull the voltage level at the pin above p3’s
trip point after some time and p3 will turn on and provide a strong ‘1’. Note, however, that
if the load exceeds the drive capability of p2 (I_IL), the pin might remain in the IL state and
provide a week 1 until the first 0-to-1 transition occurs on the latch. Until this happens,
the output level might stay below the trip point of the external circuitry.
The same is true if a pin is used as a bi-directional line and the external circuitry is
switched from output to input when the pin is held at ‘0’ and the load then exceeds the
p2 drive capabilities.
If the load exceeds I_IL, the pin can be forced to ‘1’ by writing a ‘0’ followed by a ‘1’ to the
port pin.
User’s Manual
6-11
2001-05