C508_01 Datasheet, PDF (101/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

Contents of
Timer 2
C508
On-Chip Peripheral Components
Timer Count = FFFF_H
Timer Count =
Compare Value
Timer Count = Reload Value
Interrupt can be generated
on overflow
Compare
Output
(P5.x/T2CCx)
Figure 6-17 Function of Compare Mode 0
Interrupt can be generated
on compare-match
MCD04058
6.2.2.3.2 Modulation Range of a PWM Signal in Compare Mode 0
Generally, it can be said that for every PWM generation in compare mode 0 with n-bit
wide compare registers there are 2ⁿ different settings for the duty cycle. Starting with a
constant low level (0% duty cycle) as the first setting, the maximum possible duty cycle
would then be:
(1 - 1/2ⁿ) × 100%
This means that a variation of the duty cycle from 0% to real 100% can never be reached
if the compare register and timer register have the same length. There is always a spike
which is as long as the timer clock period.
This “spike” may either appear when the compare register is set to the reload value
(limiting the lower end of the modulation range) or it may occur at the end of a timer
period. This spike in CCx register configuration of timer 2 in compare mode 0 is divided
into two halves. One half is at the beginning when the contents of the compare register
are equal to the reload value of the timer and the other half is when the compare register
is equal to the maximum value of the timer register (that is, FFFF_H). Refer to Figure 6-18
where the maximum and minimum duty cycles of a compare output signal are illustrated.
User’s Manual
6-36
2001-05