C508_01 Datasheet, PDF (43/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
External Bus Interface
4
External Bus Interface
The C508 allows for external memory expansion. The functionality and implementation
of the external bus interface are identical to the common interface for the 8051
architecture with one exception. The exception is the suppression of the ALE signal
generation when the C508 is used in systems with no external memory. Resetting the
EALE bit in SFR SYSCON gates off the ALE signal. This feature reduces RFI emissions
of the system.
4.1
Accessing External Memory
It is possible to distinguish between accesses to external program memory and
accesses to external data memory or other peripheral components. This distinction is
possible because hardware accesses to external program memory use the signal PSEN
(program store enable) as a read strobe. Accesses to external data memory use RD and
WR to strobe the memory (alternate functions of P3.7 and P3.6). Port 0 and Port 2 (with
exceptions) are used to provide data and address signals. In this section, only the Port 0
and Port 2 functions relevant to external memory accesses are described.
Fetches from external program memory always use a 16-bit address. Accesses to
external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit
address (MOVX @Ri).
4.1.1 Role of P0 and P2 as Data/Address Bus
When used to access external memory, Port 0 provides the data byte time-multiplexed
with the low byte of the address. In this state, Port 0 is disconnected from its own port
latch, and the address/data signal drives both FETs in the Port 0 output buffers. Thus, in
this application, the Port 0 pins are not open-drain outputs and do not require external
pull-up resistors.
During any access to external memory, the CPU writes FF_H to the Port 0 latch (the
special function register), thus obliterating whatever information the Port 0 SFR may
have been holding.
Whenever a 16-bit address is used, the high byte of the address comes out on Port 2,
where it is held for the duration of the read or write cycle. During this time, the Port 2 lines
are disconnected from the Port 2 latch (the special function register).
Thus, the Port 2 latch does not need to contain ‘1’s and the contents of the Port 2 SFR
are not modified.
If an 8-bit address is used (MOVX @Ri), the contents of the Port 2 SFR remain at the
Port 2 pins throughout the external memory cycle. This will facilitate paging. It should be
noted that, if a Port 2 pin outputs an address bit that is a ‘1’, strong pull-ups will be used
for the entire read/write cycle and not only for two oscillator periods.
User’s Manual
4-1
2001-05