C508_01 Datasheet, PDF (171/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
6.4.3 Baudrate Generation
There are several possibilities to generate the baudrate clock for the serial port,
depending on the mode in which it is operating.
To clarify the terminology, something should be said about the difference between
“baudrate clock” and “baudrate”.
The serial interface requires a clock rate which is 16 times the baudrate for internal
synchronization. Therefore, the baudrate generators must provide a “baudrate clock” to
the serial interface which - there divided by 16 - results in the actual “baudrate”.
However, all formulae given in the following section already include the factor and
calculate the final baudrate.
The baudrate of the serial port is controlled by two bits which are located in the special
function registers as shown below.
Special Function Register ADCON0 (Address D8_H)
Special Function Register PCON (Address 87_H)
Reset Value: 00X00000_B
Reset Value: 00_H
Bit No.
D8_H
MSB
DF_H
BD
DE_H
CLK
DD_H
–
DC_H
BSY
DB_H
ADM
DA_H
MX2
D9_H
MX1
LSB
D8_H
MX0
ADCON0
7
6
5
4
3
2
1
0
87_H SMOD PDS IDLS SD GF1 GF0 PDE IDLE PCON
The shaded bits are not used for controlling the baudrate.
Bit
BD
SMOD
–
Function
Baudrate generator enable
When set, the baudrate of the serial interface is derived from the
dedicated baudrate generator. When cleared (default after reset),
baudrate is derived from the timer 1 overflow rate.
Double baudrate
When set, the baudrate of serial interface in Modes 1, 2, 3 is doubled.
After reset this bit is cleared.
Reserved bits for future use. Read by CPU returns undefined values.
Note: Bit CLK of SFR ADCON0 must be written with a ‘0’.
User’s Manual
6-106
2001-05