C508_01 Datasheet, PDF (195/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
Sample Time t_S:
During this time, the internal capacitor array is connected to the selected analog input
channel and is loaded with the analog voltage to be converted. The analog voltage is
internally fed to a voltage comparator. At the beginning of the sample phase, the BSY bit
in SFR ADCON0 is set.
Conversion Time t_CO:
During the conversion time, the analog voltage is converted into a 10-bit digital value
using the successive approximation technique with a binary-weighted capacitor network.
During an A/D conversion, a calibration also takes place. In this calibration, alternating
offset and linearity calibration cycles are executed (see also Chapter 6.5.5). At the end
of the calibration time, the BSY bit is reset and the IADC bit in SFR IRCON is set
indicating an A/D Converter interrupt condition.
Write Result Time t_WR:
At the result phase, the conversion result is written into the ADDAT registers.
Figure 6-52 shows how an A/D conversion is embedded into the microcontroller cycle
scheme using the relation 6 × t_IN = 1 instruction cycle. It also shows the behavior of the
busy flag (BSY) and the interrupt flag (IADC) during an A/D conversion.
Prescaller
Selection
ADCL1 ADCL0
0
0
MOV ADDATL,#0
X-1 X 1
1 Instruction Cycle
23456
Write Result Cycle
MOV A, ADDATL
7 8 9 10 11 12
0
1
X-1 X 1 2 3 4 5
15 16 17 18 19 20
1
0
X-1 X 1 2 3 4 5
31 32 33 34 35 36
1
1
X-1 X 1 2 3 4 5
63 64 65 66 67 68
Start of A/D
Conversion Cycle
t_ADCC
A/D Conversion Cycle
BSY Bit
Start of next conversion
(in continuous mode)
Write
ADDAT
Cont. conv.
Single conv.
IADC Bit
First Instr. of an
Interrupt Routine
MCT04079
Figure 6-52 A/D Conversion Timing in Relation to Processor Cycles
User’s Manual
6-130
2001-05