C508_01 Datasheet, PDF (57/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Reset and System Clock Operation
5
Reset and System Clock Operation
5.1
Hardware Reset Operation
The hardware reset function incorporated in the C508 allows easy automatic startup with
minimal additional hardware and forces the controller into a predefined default state. The
hardware reset function can also be used during normal operation to restart the device.
This is particularly useful for terminating the power-down mode.
The hardware reset is applied externally to the C508. Additionally, there are three
internal reset sources: the Watchdog Timer, the Oscillator Watchdog, and the PLL. This
section deals with the external hardware reset only.
The reset input is an active high input. An internal Schmitt trigger is used at the input for
noise rejection. Since the reset is synchronized internally, the RESET pin must be held
high for at least two machine cycles (six oscillator periods) while the oscillator is running.
The internal reset is executed during the second machine cycle while the oscillator is
running and is repeated every cycle until RESET goes low again.
During reset, pins ALE and PSEN are configured as inputs and should not be stimulated
externally. (External stimulation of these lines during reset activates several reserved
test modes. This, in turn, may cause unpredictable output operations at several port
pins).
At the reset pin, a pull-down resistor is connected internally to V_SS to allow a power-up
reset using only an external capacitor. An automatic power-up reset can be obtained,
when V_DD is applied, by connecting the reset pin to V_DD via a capacitor. After V_DD has
been turned on, the capacitor must hold the voltage level at the reset pin for a specific
time to effect a complete reset.
The time required for a reset operation includes the oscillator startup time, the PLL lock
time, and the time for two machine cycles, must be at least 10 - 20 ms, under normal
conditions. This requirement is typically met using a capacitor of 4.7 to 10 µF. The same
considerations apply if the reset signal is generated externally (Figure 5-1 b). In each
case, it must be assured that the oscillator has started up properly and that at least two
machine cycles have passed before the reset signal goes inactive.
User’s Manual
5-1
2001-05