C508_01 Datasheet, PDF (58/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Reset and System Clock Operation
V_DD
+ _C508
RESET
a)
C508
&
RESET
V_DD
C508
RESET
+
b)
c)
MCS04030
Figure 5-1 Reset Circuitries
A correctly executed reset leaves the processor in a defined state. The program
execution starts at location 0000_H. After reset is internally accomplished, the port latches
of Ports 0, 1, 2, 3, and 5 default to FF_H. This leaves Port 0 floating, since it is an open
drain port when not used as data/address bus. All other I/O port lines (Ports 1, 3 and 5)
output a one (1). Port 2 lines output a zero after reset, if the EA pin is held low; or one if
EA is held high. Port 4 is a uni-directional input port. It has no internal latch; therefore,
the contents of the Special Function Register P4 depend on the levels applied to Port 4.
The internal SFRs are set to their initial states as defined in Table 3-2.
The contents of the internal RAM and XRAM of the C508 are not affected by a reset. The
contents are undefined after power-up; the contents remain unchanged during reset if
the power supply is not turned off.
User’s Manual
5-2
2001-05